Current Issue : January - March Volume : 2013 Issue Number : 1 Articles : 4 Articles
In this paper, we introduce the Reconfigurable Video Coding (RVC) standard based on the idea that video processing algorithms\r\ncan be defined as a library of components that can be updated and standardized separately. MPEG RVC framework aims at\r\nproviding a unified high-level specification of current MPEG coding technologies using a dataflow language called Cal Actor\r\nLanguage (CAL). CAL is associated with a set of tools to design dataflow applications and to generate hardware and software\r\nimplementations. Before this work, the existing CAL hardware compilers did not support high-level features of the CAL. After\r\npresenting the main notions of the RVC standard, this paper introduces an automatic transformation process that analyses the\r\nnon-compliant features and makes the required changes in the intermediate representation of the compiler while keeping the same\r\nbehavior. Finally, the implementation results of the transformation on video and still image decoders are summarized. We show\r\nthat the obtained results can largely satisfy the real time constraints for an embedded design on FPGA as we obtain a throughput\r\nof 73 FPS for MPEG 4 decoder and 34 FPS for coding and decoding process of the LAR coder using a video of CIF image size. This\r\nwork resolves the main limitation of hardware generation from CAL designs....
Modern large-scale circuit designs have created great demand for fast and high-quality global routing algorithms to resolve the\r\nrouting congestion at the global level. Rip-up and reroute scheme has been employed by the majority of academic and industrial\r\nglobal routers today, which iteratively resolve the congestion by recreating the routing path based on current congestion. This\r\nmethod is proved to be the most practical routing framework. However, the traditional iterative maze routing technique converges\r\nvery slowly and easily gets stuck at local optimal solutions. In this work, we propose a very efficient and high-quality global\r\nrouterââ?¬â?FastRoute. FastRoute integrates several novel techniques: fast congestion-driven via-aware Steiner tree construction, 3-\r\nbend routing, virtual capacity adjustment, multisource multi-sink maze routing, and spiral layer assignment. These techniques\r\nnot only address the routing congestion measured at the edges of global routing grids but also minimize the total wirelength\r\nand via usage, which is critical for subsequent detailed routing, yield, and manufacturability. Experimental results show that\r\nFastRoute is highly effective and efficient to solve ISPD07 and ISPD08 global routing benchmark suites. The results outperform\r\nrecently published academic global routers in both routability and runtime. In particular, for ISPD07 and ISPD08 global routing\r\nbenchmarks, FastRoute generates 12 congestion-free solutions out of 16 benchmarks with a speed significantly faster than other\r\nrouters....
Stereo correspondence is a popular algorithm for the extraction of depth information from a pair of rectified 2D images. Hence,\r\nit has been used in many computer vision applications that require knowledge about depth. However, stereo correspondence is a\r\ncomputationally intensive algorithm and requires high-end hardware resources in order to achieve real-time processing speed in\r\nembedded computer vision systems. This paper presents an overview of the use of edge information as a means to accelerate\r\nhardware implementations of stereo correspondence algorithms. The presented approach restricts the stereo correspondence\r\nalgorithm only to the edges of the input images rather than to all image points, thus resulting in a considerable reduction of\r\nthe search space. The paper highlights the benefits of the edge-directed approach by applying it to two stereo correspondence\r\nalgorithms: an SAD-based fixed-support algorithm and a more complex adaptive support weight algorithm. Furthermore, we\r\npresent design considerations about the implementation of these algorithms on reconfigurable hardware and also discuss issues\r\nrelated to the memory structures needed, the amount of parallelism that can be exploited, the organization of the processing\r\nblocks, and so forth. The two architectures (fixed-support based versus adaptive-support weight based) are compared in terms of\r\nprocessing speed, disparity map accuracy, and hardware overheads, when both are implemented on a Virtex-5 FPGA platform....
Two multiprocessor system-on-chip (MPSoC) architectures are proposed and compared in the paper with reference to audio and\r\nvideo processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-\r\nbit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneoustile\r\ntopology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different\r\nclass of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC) infrastructure,\r\nthrough network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and\r\nthe implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS\r\ntechnology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an\r\nH.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher\r\npower efficiency and a smaller area occupation and is more suited for low-powermultimedia processing, such as in mobile devices.\r\nThe homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP\r\ntasks in power-supplied devices....
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